1. Field of the Invention
The present invention relates to a test apparatus for testing integrated circuit chips and more particularly to a test socket for testing a plurality of bare chips to produce a plurality of known-good dies (hereinafter abbreviated to "KGD").
2. Description of the Prior Art
Standard integrated circuit chips, in general, are subjected to various tests in order to determine the reliability of the chips before distributing the chips for use. Briefly, there are two important reliability tests: one is an electrical characteristic test in which all input and output terminals are connected to a test signal generator to verify the transferring characteristics between the signals coming in and out at the terminals; and the other is a burn-in test in which a given chip is exposed to overstress conditions of higher than normal operating temperatures and voltages to verify its lifetime and to detect defects.
As an example, the burn-in test for a dynamic random access memory chip has been appreciated as a useful method to verify the reliability of memory circuit elements such as memory cells and signal lines. During the burn-in test, defects latent in a dynamic random access memory chip result in the destruction of gate oxide films of MOS transistors and shortening between multi-leveled conduction layers. These defective chips are abandoned as inferior and non-defective chips are selected instead. Since it is difficult to electrically connect a bare chip from a semiconductor wafer to the test signal generator, the tests are normally conducted by packaging the chip with external leads connected to chip pads, and inserting the external leads to a test socket, which is then mounted onto a test board. This, however, has disadvantages such as the waste of the costs for packaging a potentially inferior chip and the limitation for increasing the number of bare chips to be tested in one time.
Recently proposed and advanced integrated technologies employ a flip chip in which a plurality of bare chips are mounted on a ceramic board to yield faster operating speed, larger capacity, and integrating density than before. A multi-chip module (abbreviated to "MCM") is successfully being employed in a super computer system by several integrated circuit makers such as IBM, DEC and HITACHI with its own advantage of very large scale of integration rate. The MCM employs a plurality of chips placed onto ceramic boards including a high density arrangement of conduction lines. However, the very large scale of integration rate in the MCM technology is accompanied by technical and economical problems such as remarkably low yield, causing increased cost and decreased marketability. Though it is rigorously important to identify sufficient known-good dies (abbreviated to "KGD") of bare chips proved not to be defective, it is difficult to mass-produce the KGDs at a low cost because a single bare chip without external leads cannot be tested using the burn-in socket aforementioned or until the MCM package is mounted on a printing circuit board.
To overcome the problems described above, an apparatus is disclosed in U.S. Pat. No. 5,006,792 for providing a flip chip test socket adapter to perform the burn-in test with a bare chip, in which a plurality of solder bumps are formed on the bonding pads. The flip chip having the solder bumps on its bonding pads is inserted into the test socket adapter and is subjected to the burn-in test. The test socket adapter includes a substrate provided with cantilever beams, being accommodated within a case.
However, in the conventional test configuration, very expensive equipment must be provided to precisely form the solder bumps on the bonding pads of the IC chip because the pitches between the bonding pads are very narrow in the microscopic dimension. Furthermore, the test is performed on only one chip at a time in order to assure the reliability. Thus, the cost for one KGD may be increased and the test may not be advantageous for producing large number of the KGDs. Moreover, it is difficult to deal with single chip for an individual test of itself. In addition, the structure of the above-described socket adapter must be complicatedly changed to another configuration corresponding to another IC chip or the positions of the bumps.